1. Technical Field
The present invention relates to a method for manufacturing a memory device, and more particularly, to a method for manufacturing a memory device which avoids bit line to bit line shorts.
2. Description of the Related Art
There are a lot of contact holes formed during the formation of a DRAM, including bit line contact holes, substrate contact holes and gate contact holes. Through these contact holes, conductive wires can be formed to connect the drains, substrates and gates.
In 0.11-um CMOS processing, the width of a bit line contact hole is about 140 nm to 160 nm, and the pitch of the bit line is about 220 nm. Therefore, with miniaturization of devices, the distance between each two bit lines, between each two bit line contact holes, or between a bit line and a bit line contact hole is becoming more and more shorter, which easily causes the electric shorts and consequently results in leakage. For example, the scratches caused by chemical mechanical polishing, the stringers in the poly-silicon layer, or the offset of the bit line contact hole might produce shorts, such as bit line to bit line shorts.
FIGS. 1-2 illustrate a conventional method for manufacturing a memory device. As shown in FIG. 1, a plurality of gate structures 12 is formed on a substrate 10. The gate structure includes a cap nitride layer 14, a gate conductor 16, a gate dielectric layer 20, and a spacer 18, wherein two adjacent gate structures 12 are separated by a gap 22. Next, a polysilicon layer 24 is blanketly formed on the substrate 10 to fill the gap 22. As shown in FIG. 2, a chemical mechanical polishing (CMP) process is generally employed to remove the polysilicon layer 24 formed over the gate structure 12, forming polysilicon plugs 26. However, since the polysilicon layer formed over the gate structure 12 is not apt to be completely removed by chemical mechanical polishing, residual polysilicon may remain over the gate structure 12. Therefore, a poly stringer may be occurred, resulting in a bit-line to bit-line short after formation of a subsequent conductive layer to contact the polysilicon plugs 26.
In order to avoid the poly stringer problem, a conventional method discloses removal of the polysilicon layer 24 over the gate structure 12 via an over chemical-mechanical polishing (over CMP) process. The bit-line to bit-line short resulting from the poly stringer can be avoided by the aforementioned method. The over chemical-mechanical polishing (over CMP) process, however, undesirably removes a part of the cap nitride layer 14 (thinning the cap nitride layer), resulting in exposure of the gate conductor 16 after a subsequent etching process is conducted. Therefore, a word-line to bit-line short may be occurred after formation of a subsequent conductive layer is formed to contact with the polysilicon plugs 26.
Accordingly, a novel method for fabrication of a memory device which overcomes the above problems is desired.